CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes
Year: 2008
Type: article
Source: Nano Letters
DOI: 10.1021/nl802756u
Institutions: University of Southern California, Stanford University
Language: English
Subfield: Materials Chemistry
Field: Materials Science
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W1972577644
