Work

Formal verification using parametric representations of Boolean constraints

Year: 1999

Type: conference-paper

Abstract: We describe the use of parametric representations of Boolean predicates to encode data-space constraints and significantly extend the capacity of formal verification. The constraints are used to decompose verifications by sets of case splits and to restrict verifications by validity conditions. Our technique is applicable to any symbolic simulator. We illustrate our technique on state-of-the-art Intel(R) designs, without removing latches or modifying the circuits in any way.

Source: ACM/IEEE Design Automation Conference (DAC)

DOI: 10.1145/309847.309968

Authors: M.D. Aagaard, R.B. Jones, C.-J.H. Seger

Institution: Intel (United States)

Language: English

Topic: Formal Methods in Verification

Subfield: Computational Theory and Mathematics

Field: Computer Science

Domain: Physical Sciences

Open Access status: bronze

OpenAlex ID: W1972934510

FWCI: 5.801

Cites: 14

Cited by: 78

Related to: 10