Year: 2000
Type: article
Abstract: To narrow the widening gap between processor and memory performance, the authors propose improving the cache locality of pointer-manipulating programs and bolstering performance by careful placement of structure elements. It is concluded that considering past trends and future technology, it seems clear that the processor-memory performance gap will continue to increase and software will continue to grow larger and more complex. Although cache-conscious algorithms and data structures are the first and perhaps best place to attack this performance problem, the complexity of software design and an increasing tendency to build large software systems by assembling smaller components does not favor a focused, integrated approach. We propose another, more incremental approach of cache-conscious data layout, which uses techniques such as clustering, coloring, and compression to enhance data locality by placing structure elements more carefully in the cache.
Source: Computer
DOI: 10.1109/2.889095
Authors: J.R. Larus, M.D. Hill, T.M. Chilimbi
Institutions: Microsoft (United States), University of Wisconsin–Madison
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
Awards: NSF Young Investigator: Programming Massively-Parallel Computers, CISE Research Infrastructure: MIDSHIP: Managing Image Data for Scalable High Performance, Experimental Partnerships: Multifacet: Exploiting Prediction and Speculation in Multiprocessor Memory Systems, Tornado: Fine-Grain Distributed Shared Memory for SMP Clusters
OpenAlex ID: W1987981153