Work

A hardware peripheral for Java bytecodes translation acceleration

Year: 2010

Type: conference-paper

Abstract: Java has gained great popularity in a wide range of applications. Just-in-time compilation is crucial for providing efficient execution of Java programs, but it is generally a hard task, not suited for embedded systems. This paper presents a hardware acceleration unit for efficient execution of JIT translation in embedded SoCs. The translation is limited to only first level optimizations, which include translation of Java bytecodes to native RISC instructions (stack folding). For experimentation, we developed a SoC with ARM7TDMI processor. In a f 80nm ASIC technology and 80MHz clock, we measured a speed up of up to 4 times over the software only JIT translation.

Source: ACM Symposium on Applied Computing

DOI: 10.1145/1774088.1774201

Authors: Isidoros Sideris, Nikos Moshopoulos, Kiamal Pekmestzi

Institution: National Technical University of Athens

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W2002480685

FWCI:

Cites: 4

Cited by:

Related to: 10