Work

Cache-aware task scheduling on multi-core architecture

Year: 2010

Type: conference-paper

Source: International Symposium on VLSI Design, Automation and Test

DOI: 10.1109/vdat.2010.5496710

Authors: Teng-Feng Yang, Chung-Hsiang Lin, Chia-Lin Yang

Institutions: Institute of Information Science, Academia Sinica, Academia Sinica, National Taiwan University

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

Funders: National Science Council, National Taiwan University

OpenAlex ID: W2034476127

FWCI: 0.718

Cites: 8

Cited by: 12

Related to: 10