Work

Layout techniques for VLSI yield enhancement

Year: 2001

Type: conference-paper

Source: Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

DOI: 10.1117/12.444666

Authors: Zhan Chen, Lixin Zhang

Institution: Intel (United States)

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2050493395

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