Work

Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance

Year: 2012

Type: article

Source: Journal of Low Power Electronics

DOI: 10.1166/jolpe.2012.1207

Authors: P. S. Nair, S. Eratne, E. B. John

Institutions: California State University, Fullerton, The University of Texas at San Antonio

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2083266899

FWCI: 0.205

Cites:

Cited by: 1

Related to: 10