Year: 2010
Type: conference-paper
Abstract: We describe the architecture evolution of the highly-parallel dedicated processor FTK, which is driven by the simulation of LHC events at high luminosity (1034 cm-2 s-1). FTK is able to provide precise on-line track reconstruction for future hadronic collider experiments. The processor, organized in a two-tiered pipelined architecture, execute very fast algorithms based on the use of a large bank of pre-stored patterns of trajectory points (first tier) in combination with full resolution track fitting to refine pattern recognition and to determine off-line quality track parameters. We describe here how the high luminosity simulation results have produced a new organization of the hardware inside the FTK processor core.
Authors: A. Annovi, M. Beretta, P. Laurelli, E. Bossini, V. Cavasinni, F. Crescioli, M. Dell'Orso, P. Giannetti, M. Piendibene, G. Punzi, F. Sarri, I. Vivarelli, G. Volpi, L. Sartori, A. Boveia, E. Brubaker, F. Canelli, M. Dunford, A. Kapliy, Y. K. Kim, C. Melachrinos, M. Shochet, J. Tuggle, H. DeBerg, A. McCarn, M. Neubauer, M. Franklin, C. Mills, N. Kimura, K. Yorita, J. Proudfoot, J. Zhang, R. Tripiccione
Institutions: Istituto Nazionale di Fisica Nucleare, Laboratori Nazionali di Frascati, Istituto Nazionale di Fisica Nucleare, Istituto Nazionale di Fisica Nucleare, Sezione di Pisa, University of Chicago, University of Illinois Urbana-Champaign, Harvard University, Waseda University, Argonne National Laboratory, University of Ferrara, Istituto Nazionale di Fisica Nucleare, Sezione di Ferrara
Language: English
Subfield: Nuclear and High Energy Physics
Field: Physics and Astronomy
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W2086912237