Work

Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review

Year: 2004

Type: article

Abstract: This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

Source: IEEE Transactions on Device and Materials Reliability

DOI: 10.1109/tdmr.2004.824359

Authors: A. Chaudhry, M.J. Kumar

Institution: Indian Institute of Technology Delhi

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W2096227378

FWCI: 9.485

Cites: 81

Cited by: 498

Related to: 10