Work

Universal-V/sub dd/ 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

Year: 2001

Type: article

Source: IEEE Journal of Solid-State Circuits

DOI: 10.1109/4.962296

Authors: K. Osada, Jinuk Luke Shin, M. Khan, Y. Liou, K. Wang, K. Shoji, K. Kuroda, S. Ikeda, K. Ishibashi

Institution: Hitachi (Japan)

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2111701388

FWCI: 4.601

Cites: 10

Cited by: 81

Related to: 10