Work

A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS

Year: 2012

Type: conference-paper

Source: Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

DOI: 10.1109/isscc.2012.6176995

Authors: Nathaniel August, Hyung-Jin Lee, Martin Vandepas, Rachael Parker

Institution: Intel (United States)

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2112008043

FWCI: 11.38

Cites: 8

Cited by: 60

Related to: 10