Work

Augmenting loop tiling with data alignment for improved cache performance

Year: 1999

Type: article

Source: IEEE Transactions on Computers

DOI: 10.1109/12.752655

Authors: P.R. Panda, H. Nakamura, N.D. Dutt, A. Nicolau

Institutions: Synopsys (United States), Research Center for Advanced Science and Technology, The University of Tokyo, The University of Tokyo, University of California, Irvine

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

Funder: National Science Foundation

OpenAlex ID: W2116493917

FWCI: 10.77

Cites: 15

Cited by: 100

Related to: 10