Transformation and VHDL Code Generation from Coarse-grained Dataflow Graph
Year: 1998
Type: article
Abstract: This paper discusses how we generate VHDL codes for DSP applications described in dataflow graphs. Because the generated VHDL code implements the details of the control structure, we can easily transform it into a running circuit without any modifications, using logic synthesis tools. To improve the quality of the synthesized circuit we apply some graph transformation techniques to the original dataflow graph. We mainly consider coarse-grained dataflow graphs in which each node corresponds to an IP component of considerable size. The proposed facility is very useful for dataflow graph based high level design tools, including our codesign framework PeaCE (Ptolemy extension as Codesign Environment).
Authors: Moonwook Oh, Soonhoi Ha
Institution: Seoul National University
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W2128319049