Year: 1999
Type: article
Abstract: With recent advances in silicon device technology, a new branch of computer architecture, recon gurable computing, has emerged.While this computing domain holds the promise of exceptional ne-grained parallel performance, the amount of time required to compile a program to a recon gurable computing platform can be prohibitive for many applications.A large portion of this compile time is typically spent performing device layout for eld-programmable gate arrays (FPGAs), the core hardware components of most recon gurable computing systems.In this thesis, an new integrated oorplanning and routing system for FPGAs, called Frontier, is detailed.This system has been designed to optimize FPGA layout time at the cost of modest increases in device logic and routing resources.Experimental results are presented which demonstrate an order of magnitude speedup over traditional layout approaches for an island-style FPGA architecture.A k ey part of the Frontier system is a depth-rst router that signi cantly reduces the search space required for FPGA routing and leads to decreased run time when compared to a traditional, breadthrst maze router.In the thesis, it is shown that for the depth-rst case, the sparse nature of planar switchboxes, found in many island-style architectures, necessitates an additional localized search near net inputs, called domain negotiation, to aid in directing the route of each design net onto a set of routing resources most likely to lead to a successful route.This router is tightly coupled with a macro-based oorplanner based on hierarchical, slicing approaches.The oorplanner takes advantage of a set of pre-placed and pre-routed macro-blocks that are commonly found in a broad range of computing applications.The depth-rst router can be used to rapidly identify congestion in the oorplan and drive a feedback-driven placement relaxation phase.The use of an FPGA oorplanner provides an opportunity to evaluate techniques that isolate intra-macro routing from inter-macro connectivity i n w ays typically found in ASIC design styles.By following this design style, macro-sized pieces of a user design layout may be replaced without the need to re-place or re-route signi cant portions of the design.
Authors: Russell Tessier, Stephen A. Ward
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W2130950765