VERIFY: evaluation of reliability using VHDL-models with embedded fault descriptions
Year: 2002
Type: conference-paper
Authors: V. Sieh, O. Tschache, F. Balbach
Institution: Friedrich-Alexander-Universität Erlangen-Nürnberg
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2135577965