Work

An all-digital phase-locked loop for high-speed clock generation

Year: 2003

Type: article

Source: IEEE Journal of Solid-State Circuits

DOI: 10.1109/jssc.2002.807398

Authors: Ching-Che Chung, Chen-Yi Lee

Institution: National Yang Ming Chiao Tung University

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: National Science Council, National Chiao Tung University

OpenAlex ID: W2137120286

FWCI: 8.036

Cites: 13

Cited by: 207

Related to: 10