Work

A formal executable semantics of Verilog

Year: 2010

Type: conference-paper

Abstract: This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilog-based tools; e.g., simulators, test generators, and verification tools. Our semantics applies equally well to both synthesizeable and behavioral designs and is given in a familiar, operational-style within a logic providing important additional benefits above and beyond static formalization. In particular, it is executable and searchable so that one can ask questions about how a, possibly nondeterministic, Verilog program can legally behave under the formalization. The formalization should not be seen as the final word on Verilog, but rather as a starting point and basis for community discussions on the Verilog semantics.

Source: ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE)

DOI: 10.1109/memcod.2010.5558634

Authors: Patrick Meredith, Michael Katelman, Jose Meseguer, Grigore Rosu

Institution: University of Illinois Urbana-Champaign

Language: English

Topic: Logic, programming, and type systems

Subfield: Software

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

Funders: National Science Foundation, National Aeronautics and Space Administration

Awards: TC: Medium: Collaborative Research: Rewriting Logic Foundations for Verification and Programming of Next-Generation Trustworthy Web-Based Systems, CAREER: Runtime Verification and Monitoring, CSR-EHS: Monitor and Control: Towards Dependable COTS-based Real-Time Embedded Systems, SHF: Small: IMUnit: Improved Multithreaded Unit Testing