Work

Model-Based Test Suite Generation for Function Block Diagrams Using the UPPAAL Model Checker

Year: 2013

Type: conference-paper

Abstract: A method for model-based test generation of safety-critical embedded applications using Programmable Logic Controllers and implemented in a programming language such as Function Block Diagram (FBD) is described. The FBD component model is based on the IEC 1131 standard and it is used primarily for embedded systems, in which timeliness is an important property to be tested. Our method involves the transformation of FBD programs with timed annotations into timed automata models which are used to automatically generate test suites. Specifically we demonstrate how to use model transformation for formalization and model-checking of FBD programs using the UPPAAL tool. Many benefits emerge from this method, including the ability to automatically generate test suites from a formal model in order to ensure compliance to strict quality requirements including unit testing and specific coverage measurements. The approach is experimentally assessed on a train control system in terms of consumed resources.

Source: IEEE International Conference on Software Testing, Verification and Validation Workshops (ICSTW)

DOI: 10.1109/icstw.2013.27

Authors: Eduard Paul Enoiu, Daniel Sundmark, Paul Pettersson

Institution: Mälardalen University

Language: English

Topic: Formal Methods in Verification

Subfield: Computational Theory and Mathematics

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W2153268462

FWCI: 5.959

Cites: 24

Cited by: 45

Related to: 10