Work

On estimation and optimization of leakage power in CMOS multipliers

Year: 2007

Type: conference-paper

Source: IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

DOI: 10.1109/mwscas.2007.4488708

Authors: D. Kudithipudi, P. Nair, E. John

Institutions: Rochester Institute of Technology, The University of Texas at San Antonio

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2163961199

FWCI:

Cites: 3

Cited by: 1

Related to: 10