Reducing compilation time of Zhong's FPGA-based SAT solver
Year: 2003
Type: conference-paper
Authors: P.K. Chan, M.J. Boyd, S. Goren, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu
Institution: University of California, Santa Cruz
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2166645839
