1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
Year: 2002
Type: article
Source: IEEE Electron Device Letters
Authors: R. Rengarajan, Boyong He, C. Ransom, Chang Ju Choi, R. Ramachandran, Haining Yang, S. Butt, S. Halle, W. Yan, K. Lee, M. Chudzik, W. Robl, C. Parks, J.G. Massey, G. La Rosa, Yujun Li, C. Radens, R. Divakaruni, E. Crabbe
Institution: IBM (United States)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2171007056