Work

A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology

Year: 2015

Type: conference-paper

Source: IEEE Custom Integrated Circuits Conference (CICC)

DOI: 10.1109/cicc.2015.7338432

Authors: Amr Lotfy, Syed Feruz Syed Farooq, Qi S Wang, Soner Yaldiz, Praveen Mosalikanti, Nasser Kurd

Institution: Intel (United States)

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2180303965

FWCI: 1.234

Cites: 9

Cited by: 13

Related to: 10