Year: 2011
Type: conference-paper
Abstract: Here we examine photolithography methodologies to improve the efficiency of foundry and ASIC manufactures that have many part numbers with relatively low run volumes. In such cases, a fab must accommodate a large variety of device layers, topography dispersion, and layout parameters. These factors reduce the lithography process margin and limit design freedom and throughput in the lithography module. These factors also increase design complexity, optical proximity correction (OPC) design loops, mask cost, exposure dose, and number of material sets to meet layer requirements. Consequently, these factors impact the fab's overall efficiency. The primary method proposed to improve efficiency is to use a system that includes a planarizing etch transfer layer, an image transfer layer, and an image capture layer. By combining these elements, the lithography process becomes very predictable, simple, and repeatable, independent of the device
Source: ECS Transactions
DOI: 10.1149/1.3567588
Authors: James E. Lamb, Cox Chris, Zhimin Zhu, David Drain, Daniel Sullivan
Institution: Brewer Science (United States)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W2312494192