Work

Reducing Power and Cycle Requirement for Fast Fourier Transform of Electrocardiogram Signals Through Low Level Arithmetic Optimizations for Cardiac Implantable Devices

Year: 2016

Type: article

Abstract: N) algorithm which requires complex multiplication and addition using floating point numbers. On extremely power constrained embedded systems such as cardiac pacemakers, floating point operations are very cycle intensive and costly in terms of power. This work aims to exploit the repetitive nature of the Electrocardiogram (ECG) to reduce the number of total arithmetic operations required to execute a 128 point FFT routine. Using the simple concept of lookup tables, the proposed algorithm is able to improve both the performance and energy footprint for computing the FFT of the ECG data. An increase of 9.22% in computational speed and an improvement of 10.1% in battery life on a 32 bit embedded platform for a standard split-radix-2 FFT routine is achieved. The concept is tested using actual ECG data collected from PhysioNet.

Source: Journal of Low Power Electronics

DOI: 10.1166/jolpe.2016.1423

Authors: Safwat Mostafa, Eugene John

Institution: The University of Texas at San Antonio

Language: English

Topic: Digital Filter Design and Implementation

Subfield: Signal Processing

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

Funder: National Institute of General Medical Sciences

Award: Ultra Low Power Integrated Circuits and Systems for Cardiac Pacemakers