Work

Random modulo

Year: 2016

Type: conference-paper

Abstract: Cache memories have a huge impact on software's worst-case execution time (WCET). While enabling the seamless use of caches is key to provide the increasing levels of (guaranteed) performance required by automotive software, caches complicate timing analysis. In the context of Measurement-Based Probabilistic Timing Analysis (MBPTA) -- a promising technique to ease timing analyis of complex hardware -- we propose Random Modulo (RM), a new cache design that provides the probabilistic behavior required by MBPTA and with the following advantages over existing MBPTA-compliant cache designs: (i) an outstanding reduction in WCET estimates, (ii) lower latency and area overhead, and (iii) competitive average performance w.r.t conventional caches.

Source: ACM/IEEE Design Automation Conference (DAC)

DOI: 10.1145/2897937.2898076

Authors: Carles Hernandez, Jaume Abella, Andrea Gianarro, Jan Andersson, Francisco J. Cazorla

Institutions: Barcelona Supercomputing Center, Consejo Superior de Investigaciones Científicas, Artificial Intelligence Research Institute

Language: English

Topic: Real-Time Systems Scheduling

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

Funders: Ministerio de Economía y Competitividad, Seventh Framework Programme

Awards: G3324247440, G4019578423, G5592594182, G8257141572