Work

Global Optimization Algorithms for Chip Layout and Compaction

Year: 1995

Type: article

Source: Engineering Optimization

DOI: 10.1080/03052159508941259

Authors: MICHAEL C. DORNEICH, NIKOLAOS V. SAHINIDIS

Institution: University of Illinois Urbana-Champaign

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2509864001

FWCI: 1.436

Cites: 34

Cited by: 83

Related to: 10