Work

Design of high speed CRC algorithm for ethernet on FPGA using reduced lookup table algorithm

Year: 2016

Type: conference-paper

Source: IEEE India Conference

DOI: 10.1109/indicon.2016.7839009

Authors: Bajarangbali, P. Aparna Anand

Institution: PES University

Language: English

Topic: Embedded Systems and FPGA Applications

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2583490885

FWCI: 5.623

Cites: 11

Cited by: 21

Related to: 10