Year: 2005
Type: article
Abstract: In order to obtain continued performance improvements from microprocessors, ways must be found to increase the degree of parallel execution. However, the parallelism of single-threaded programs is limited by the control flow within the code. This paper proposes a technique to reduce the control flow bottleneck by observing that much of the control flow computation can be performed in parallel with data computation. Using this observation the program can be partitioned into a control flow generating portion, called the control thread, and a data computing portion, broken up into work threads. This paper further proposes an architecture to execute the control and work threads in parallel. After a detailed microarchitecture simulation, we observe a perfomance speedup of 1.03 to 1.48 on integer benchmarks, with an average of 1.16 on a dual 4-wide versus a conventional 4-wide superscalar processor, and an average of 1.20 on a dual 8-wide versus a single 8-wide superscalar processor. 1.
Authors: Aqeel Mahesri, Sanjay J. Patel
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W2594739744