Work

Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing

Year: 2017

Type: article

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI: 10.1109/tcad.2017.2685598

Authors: Mark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin, Nai-Chen Chen

Institution: National Chung Cheng University

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: Ministry of Science and Technology, Taiwan, National Cheng Kung University

Awards: Ratioed Capacitor Layout Synthesis Considering Matching and Parasitic Effects, Next Generation Analog Layout Synthesis Methodologies

OpenAlex ID: W2603623014

FWCI: 0.933

Cites: 22

Cited by: 24

Related to: 10