Year: 2005
Type: article
Abstract: In the past few decades with advancement in VLSI technology, FPGA chip density has increased and FPGA devices now provide a large number of smaller feature size transistors and can support higher clock speeds.While this advancement is beneficial for implementing larger and faster designs within a single chip, it also leads to increased power consumption.With the remarkable growth of FPGA based battery-powered systems, such as personal computing devices, wireless equipment, space-borne systems, and consumer electronics, low power FPGA design is of increased importance.In this thesis, I investigate various FPGA design techniques to minimize dynamic power consumed by an FPGA design.The objective of this research is to minimize the power drawn by a design without altering its functionality and with minimal or no impact on its timing.The work focuses on the implementation of control logic within a design.Reduction of power consumption of an FPGA design is attempted at the following design stages: high-level synthesis, mapping and placement and routing stage.In addition, power consumed by fault tolerant finite state machines in FPGAs is also addressed, and it has been shown that power consumed by the proposed alternate design is significantly lower than a traditional fault tolerant design.The central idea behind all the design techniques proposed is to reduce the switching activity on the power hungry programmable interconnection network.Power consumed by the clock network which also consumes a considerable amount of power is also reduced by selective clocking of finite state machines.The techniques and algorithms presented in this thesis can be easily automated and can be incorporated in an existing FPGA design flow.
Author: Anurag Tiwari
Institution: University of Cincinnati
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W2603949163