Work

EFTEM studies on the localization of silicon nanocrystals embedded in SiO2 for nano-devices

Year: 2012
Type: conference-paper
Abstract: Silicon nanocrystals (Si Ncs) based devices attract a strong interest thanks to their potential application in microelectronic and opto-electronic domains [1]. Si Ncs help to overcome downscaling limitations of the standard floating gate used in non-volatile memory devices [2-3]. In particular, the use of a multi-node charge storage provided by a Si Ncs array is beneficial to get improved retention and programming at lower voltage [4]. Because a strong correlation exists between structural characteristics and electrical properties of nanomaterials, an accurate control of the synthesis process in relation with the Ncs characteristics such as size, density and organization is necessary for their development. 2D array of Si Ncs embedded in thin SiO2 layer with controlled size, density and depth have been demonstrated for different techniques like CVD [5], MBE and Ion Beam Synthesis (IBS) [6]. In particular, in the past decade, operating non-volatile memory and optoelectronic devices have been fabricated by the Ultra-low energy (ULE)-IBS followed by thermal annealing [6, 7]. Downscaling, i.e. reducing the effect of fluctuations while the number of Ncs involved in the device becomes small requires that the localization of the Ncs within the plane should be precisely controlled [8]. For this purpose, we investigated for the first time the capabilities of combining Si NCs fabrication
Source: HAL
Language: English
Open Access status: green
OpenAlex ID: W2785047633
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