Work

A 0.009 mm2 Wide-Tuning Range Automatically Placed-and-Routed ADPLL in 14-nm FinFET CMOS

Year: 2018

Type: article

Source: IEEE Solid-State Circuits Letters

DOI: 10.1109/lssc.2018.2827880

Authors: David M. Moore, Thucydides Xanthopoulos, Scott Meninger, David D. Wentzloff

Institution: University of Michigan

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2801898480

FWCI: 0.955

Cites: 10

Cited by: 17

Related to: 10