Work

PCH framework for IP runtime security verification

Year: 2017

Type: conference-paper

Abstract: Untrusted third-party vendors and manufacturers have raised security concerns in hardware supply chain. Among all existing solutions, formal verification methods provide powerful solutions in detection malicious behaviors at the pre-silicon stage. However, little work have been done towards built-in hardware runtime verification at the post-silicon stage. In this paper, a runtime formal verification framework is proposed to evaluate the trust of hardware during its execution. This framework combines the symbolic execution and SAT solving methods to validate the user defined properties. The proposed framework has been demonstrated on an FPGA platform using an SoC design with untrusted IPs. The experimentation results show that the proposed approach can provide high-level security assurance for hardware at runtime.

Source: Asian Hardware Oriented Security and Trust Symposium (AsianHOST)

DOI: 10.1109/asianhost.2017.8353999

Authors: Xiaolong Guo, Raj Gautam Dutta, Jiaji He, Yier Jin

Institutions: University of Florida, University of Central Florida, Tianjin University

Language: English

Topic: Physical Unclonable Functions (PUFs) and Hardware Security

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W2803023250

FWCI: 0.337

Cites: 32

Cited by: 7

Related to: 10