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A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications

Year: 2018

Type: conference-paper

Source: IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)

DOI: 10.1109/coolchips.2018.8373084

Authors: Kesami Hagiwara, Tomoichi Hayashi, Shumpei Kawasaki, Fumio Arakawa, Oleg Endo, Hayato Nomura, Akira Tsukamoto, Duong Nguyen, Binh Nguyen, Anh Tran, Hoan Hyunh, Ikuo Kudoh, Cong-Kha Pham

Institutions: University of Electro-Communications, Nagoya University, The University of Tokyo

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2807235401

FWCI: 0.365

Cites: 1

Cited by: 8

Related to: 10