Work

Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell

Year: 2018

Type: article

Source: IEEE Transactions on Electron Devices

DOI: 10.1109/ted.2018.2879788

Authors: Binh Q. Le, Alessandro Grossi, Elisa Vianello, Tony Wu, Giusy Lama, Edith Beigne, H.-S. Philip Wong, Subhasish Mitra

Institutions: Stanford SystemX Alliance, Stanford University, Commissariat à l'Énergie Atomique et aux Énergies Alternatives, CEA Grenoble, Laboratoire d'Électronique des Technologies de l'Information

Language: English

Topic: Advanced Memory and Neural Computing

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: Stanford SystemX Alliance, Defense Advanced Research Projects Agency

OpenAlex ID: W2902880618

FWCI: 2.351

Cites: 13

Cited by: 66

Related to: 10