OpenAlex | TeLEx: learning signal temporal logic from positive examples using tightness metric

TeLEx: learning signal temporal logic from positive examples using tightness metric

Work

Year: 2019

Type: article

Source: Formal Methods in System Design

Authors Susmit Jha, Ashish Tiwari, Sanjit A. Seshia, Tuhin Sahai, Natarajan Shankar

Institutions SRI International, Menlo School, University of California, Berkeley

Cites: 40

Cited by: 37

Related to: 10

FWCI: 4.081

Citation percentile (by year/subfield): 91.68

Topic: Machine Learning and Algorithms

Subfield: Artificial Intelligence

Field: Computer Science

Domain: Physical Sciences

Sustainable Development Goal Peace, justice, and strong institutions

Open Access status: closed

Funders Directorate for Computer and Information Science and Engineering, Directorate for Computer and Information Science and Engineering, Army Research Laboratory

Grant IDS 1750009, CNS-1740079, US ARL Cooperative Agreement W911NF-17- 2-0196