Work

Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction

Year: 2019

Type: conference-paper

Source: Lecture notes in computer science

DOI: 10.1007/978-3-030-20652-9_11

Authors: Aman Goel, Karem Sakallah

Institution: University of Michigan

Language: English

Topic: Formal Methods in Verification

Subfield: Computational Theory and Mathematics

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2947455595

FWCI: 2.344

Cites: 45

Cited by: 36

Related to: 10