Work

Circuit Partitioning optimization using Parallel refinement algorithm

Year: 2018

Type: conference-paper

Source: IEEE International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC)

DOI: 10.1109/aespc44649.2018.9033291

Authors: Suryakanta Nayak, Satyasen Panda, Mrutyunjaya Panda

Institutions: Utkal University, Gandhi Institute for Technological Advancement

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W3011252665

FWCI:

Cites: 8

Cited by: 1

Related to: 10