Year: 2020
Type: conference-paper
Abstract: The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase 2 CMS Outer Tracker at the High-Luminosity LHC (HL-LHC). Prototyped in a 65 nm CMOS technology, the CIC aggregates the digital data coming from eight upstream front-end chips, formatting it into data packets containing the trigger information from eight bunch crossings and the raw data from events passing the Level 1 (L1) trigger, before transmission to the lpGBT. The role of the CIC in the readout chain is to provide an extra factor of data reduction by grouping data over time and space. A first prototype, the CIC1, integrating all functionalities for system level operation, has been tested in early 2019. A brief description of the functionalities and the test results obtained concerning the performance characterization and the radiation tolerance of the chip are presented in this contribution.
DOI: 10.22323/1.370.0102
Institutions: Institut de Physique, Institut de Physique des 2 Infinis de Lyon, Centre National de la Recherche Scientifique, Institut National de Physique Nucléaire et de Physique des Particules, European Organization for Nuclear Research, Vrije Universiteit Brussel, École Polytechnique Fédérale de Lausanne, University of Bristol
Language: English
Subfield: Nuclear and High Energy Physics
Field: Physics and Astronomy
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W3018029810