Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning
Year: 2020
Type: article
Institutions: Ohio University, George Washington University
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
Funder: National Science Foundation
Awards: SHF: Medium: Collaborative Research: Photonic Neural Network Accelerator for Energy-efficient Heterogeneous Multicore Architectures, SaTC: CORE: Small: Language Abstractions for Reconfigurable Hardware Monitors on Manycore Architectures, SHF: Small: Collaborative Research: Integrated Framework for System-Level Approximate Computing, SHF: Medium: Collaborative Research: Machine Learning Enabled Network-on-Chip Architectures for Optimized Energy, Performance and Reliability, SHF: Medium: Collaborative Research: Scaling On-chip Networks to 1000-core Systems using Heterogeneous Emerging Interconnect Technologies, SHF: Medium: Collaborative Research: Scaling On-chip Networks to 1000-core Systems using Heterogeneous Emerging Interconnect Technologies, SHF: Medium: Collaborative Research: Machine Learning Enabled Network-on-Chip Architectures Optimized for Energy, Performance and Reliability
OpenAlex ID: W3091302632