Design and Verification of Dual Logic Lasmas State Machine for Soc
Year: 2020
Type: article
Abstract: The dual-core embedded System-on-Chip (SoC) will be used especially in high processing
demands such as video processing, audio processing and sometimes mixing of both audio processing and video
processing. On a single chip it can design two processor cores and different interfaces to restrict a bus known as
128-bit ARM advanced microcontroller bus architecture AMBA. The Lasmas state machine output can able to
determine the time of latch level produced by the register. The coordination of the bus and to implementation
some responsive functions will be developed by the RISC (reduced-instruction-set computing) core. The
development of transformational tasks with better accuracy and regular behavior can be implemented by DSP
(digital signal processing) core. The DSP design can be enhanced to a great extent by executing all these tasks.
The Transport Triggered Architecture (TTA) is used to design a DSP core which can minimize the hardware
complexity, increase the flexibility and reduce the market time to a greater extent. This system will be expected
to give optimum performance at suitable operating frequency. Finally it will consume very less amount of
power. The design and implementation of dual logic Lasmas state machine for SoC will be implemented using
TTA-DSP architecture.
Source: Journal of Critical Reviews
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W3110417997