Work

A PLL clock generator with 5 to 110 MHz of lock range for microprocessors

Year: 1992

Type: article

Source: IEEE Journal of Solid-State Circuits

DOI: 10.1109/4.165341

Authors: I.A. Young, J.K. Greason, K.L. Wong

Institution: Intel (United States)

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W3142075743

FWCI: 7.88

Cites: 5

Cited by: 417

Related to: 10