Year: 2021
Type: conference-paper
Abstract: In this paper, we present GradPIM, a processingin-memory architecture which accelerates parameter updates of deep neural networks training. As one of processing-in-memory techniques that could be realized in the near future, we propose an incremental, simple architectural design that does not invade the existing memory protocol. Extending DDR4 SDRAM to utilize bank-group parallelism makes our operation designs in processing-in-memory (PIM) module efficient in terms of hardware cost and performance. Our experimental results show that the proposed architecture can improve the performance of DNN training and greatly reduce memory bandwidth requirement while posing only a minimal amount of overhead to the protocol and DRAM area.
Authors: Heesu Kim, Hanmin Park, Taehyun Kim, Kwanheum Cho, Eojin Lee, Soojung Ryu, Hyuk-Jae Lee, Kiyoung Choi, Jinho Lee
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
Funders: Samsung Advanced Institute of Technology, National Research Foundation, Yonsei University, Ministry of Trade, Industry and Energy, National Research Foundation of Korea, Ministry of Science and ICT, South Korea, Samsung, Korea Evaluation Institute of Industrial Technology, Institute for Information and Communications Technology Promotion
OpenAlex ID: W3158634533