Work

Graph-Model-Based Generative Layout Optimization for Heterogeneous SiC Multichip Power Modules With Reduced and Balanced Parasitic Inductance

Year: 2022

Type: article

Source: IEEE Transactions on Power Electronics

DOI: 10.1109/tpel.2022.3157873

Authors: Yu Zhou, Yuting Jin, Yu Chen, Haoze Luo, Wuhua Li, Xiangning He

Institution: Zhejiang University

Language: English

Topic: Silicon Carbide Semiconductor Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funders: National Natural Science Foundation of China, National Science Fund for Distinguished Young Scholars

Awards: G4577137915, G5471607881, G6570374497

OpenAlex ID: W4226359142

FWCI: 1.942

Cites: 41

Cited by: 36

Related to: 10