Work

Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories

Year: 2002

Type: conference-paper

Abstract: Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across applications. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instruction caches. We propose, gated-V/sub dd/, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-V/sub dd/ together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.

Source: International Symposium on Low Power Electronics and Design (ISLPED)

DOI: 10.1109/lpe.2000.876763

Authors: M. Powell, Se-Hyun Yang, B. Falsafi, K. Roy, T.N. Vijaykumar

Institution: Purdue University West Lafayette

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: green

Funders: National Science Foundation, Defense Advanced Research Projects Agency