Work

A low-overhead coherence solution for multiprocessors with private cache memories

Year: 1984

Type: conference-paper

Abstract: This paper presents a cache coherence solution for multiprocessors organized around a single time-shared bus. The solution aims at reducing bus traffic and hence bus wait time. This in turn increases the overall processor utilization. Unlike most traditional high-performance coherence solutions, this solution does not use any global tables. Furthermore, this coherence scheme is modular and easily extensible, requiring no modification of cache modules to add more processors to a system. The performance of this scheme is evaluated by using an approximate analysis method. It is shown that the performance of this scheme is closely tied with the miss ratio and the amount of sharing between processors.

Source: Proceedings - International Symposium on Computer Architecture/Proceedings

DOI: 10.1145/800015.808204

Authors: Mark S. Papamarcos, Janak H. Patel

Institutions: University of Illinois Urbana-Champaign, University of Illinois at Springfield

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: bronze

OpenAlex ID: W4249203857

FWCI: 3.463

Cites: 10

Cited by: 244

Related to: 10