Work

A Novel Fault-Tolerant Logic Style with Self-Checking Capability

Year: 2022

Type: conference-paper

Abstract: We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for each rail of outputs enables construction of fault-tolerant configurable circuits. The AND and OR gates consist of 8 transistors based on CNFET technology, while the proposed XOR gate benefits from both CNFET and low-power MGDI technologies in its transistor arrangement. To demonstrate the feasibility of our new logic gates, we used an AES S-box implementation as the use case. The extensive simulation results using HSPICE indicate that the case-study circuit using on proposed gates has superior speed and power consumption compared to other implementations with error-detection capability.

Source: IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)

DOI: 10.1109/iolts56730.2022.9897818

Authors: Mahdi Taheri, Saeideh Sheikhpour, Ali Mahani, Maksim Jenihhin

Institutions: Tallinn University of Technology, Ghent University, Shahid Bahonar University of Kerman

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: green

Funders: European Commission, Eesti Teadusagentuur, European Social Fund

Awards: CRASHLESS - Cross-Layer Reliability and Self-Health Awareness for Intelligent Autonomous Systems, G900587751