Year: 2023
Type: preprint
Abstract: Ternary logic is expected to increase the area efficiency of VLSI due to its expressiveness compared to the traditional binary logic. This paper proposes a new symmetric ternary logic and a systematic logic composition methodology that enables us to design any ternary logic circuits. The methodology is demonstrated by implementing the ternary inverters, ternary NAND, ternary NOR, and ternary half-adder operators with the proposed symmetric ternary operators.
Source: arXiv (Cornell University)
Author: Kawashima, Ichiro
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4375957901
