Year: 2023
Type: preprint
Abstract: We discuss three SYCL realisations of a simple Finite Volume scheme over multiple Cartesian patches. The realisation flavours differ in the way how they map the compute steps onto loops and tasks: We compare an implementation that is exclusively using a sequence of for-loops to a version that uses nested parallelism, and finally benchmark these against a version modelling the calculations as task graph. Our work proposes realisation idioms to realise these flavours within SYCL. The results suggest that a mixture of classic task and data parallelism performs if we map this hybrid onto a solely data-parallel SYCL implementation, taking into account SYCL specifics and the problem size.
Source: arXiv (Cornell University)
Authors: Loi, Chung Ming, Bockhorst, Heinrich, Weinzierl, Tobias
Institutions: Durham University, Intel (Germany)
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
Awards: Durham DiRAC-2 petascale facility, G1468651527, DiRAC-2.5 - the pathway to DiRAC Phase 3, G2309215924, G2368581224, G2724489712, G2843074508, G3403823835, G41932317, G4251892262, An ExCALIBUR Multigrid Solver Toolbox for ExaHyPE, G4831232377, G5554892693, DiRAC-2.5 DC - Operations 2017-2020, G6537386148, G6873874887, Particles At eXascale on High Performance Computers (PAX-HPC), DiRAC: Memory Intensive 2.5y, G8986044568, DiRAC: Memory Intensive 2.5x
OpenAlex ID: W4382765723