Work

Gate--Level Statistical Timing Analysis: Exact Solutions, Approximations and Algorithms

Year: 2024

Type: preprint

Abstract: In this paper, the Statistical Static Timing Analysis (SSTA) is considered within the block--based approach. The statistical model of the logic gate delay propagation is systematically studied and the exact analytical solution is obtained, which is strongly non-Gaussian. The procedure of handling such (non-Gaussian) distributions is described and the corresponding algorithm for the critical path delay is outlined. Finally, the proposed approach is tested and compared with Monte Carlo simulations.

Source: arXiv (Cornell University)

DOI: 10.48550/arxiv.2401.03588

Authors: Mishagli, Dmytro, Koskin, Eugene, Blokhina, Elena

Institution: University College Dublin

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: green

Funders: Science Foundation Ireland, European Regional Development Fund

Awards: G6586979110, CONNECT: The Centre for Future Networks & Communications

OpenAlex ID: W4390722541

Cites:

Cited by:

Related to: 10